1. Field of the Invention
The present invention relates to a semiconductor device having a trench gate VDMOSFET and a method of manufacturing a semiconductor device.
2. Description of Related Art
A trench gate structure is generally known as a structure effective for refinement of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor).
FIG. 9 is a schematic sectional view of a conventional semiconductor device 100 having a trench gate VDMOSFET.
The semiconductor device 100 includes an N+-type substrate 101. An N−-type epitaxial layer 102 is laminated on the N+-type substrate 101. The base layer portion of the N−-type epitaxial layer 102 forms an N−-type region 103, while a P−-type body region 104 is formed on the surface layer portion of the N−-type epitaxial layer 102 vertically adjacently to the N−-type region 103.
A gate trench 105 is dug in the N−-type epitaxial layer 102 from the surface thereof. The gate trench 105 passes through the P−-type body region 104, so that the deepest portion thereof reaches the N−-type region 103. A gate electrode 107 made of polysilicon doped with an N-type impurity in a high concentration is embedded in the gate trench 105 through a gate insulating film 106 made of SiO2 (silicon oxide).
An N+-type source region 108 is formed on the surface layer portion of the P−-type body region 104 along the gate trench 105. A P+-type contact region 109 is formed at the center of the N+-type source region 108 in plan view, to pass through the N+-type source region 108.
An interlayer dielectric film 110 is laminated on the N−-type epitaxial layer 102. A source wire 111 is formed on the interlayer dielectric film 110. This source wire 111 is grounded. The source wire 111 is in contact (electrically connected) with the N+-type source region 108 and the P+-type contact region 109 through a contact hole 112 formed in the interlayer dielectric film 110. A gate wire 113 is electrically connected to the gate electrode 107 through another contact hole (not shown) formed in the interlayer dielectric film 110.
A drain electrode 114 is formed on the back surface of the N+-type substrate 101.
A current can be fed between the N+-type source region 108 and the drain electrode 114 by controlling the potential of the gate electrode 107 while applying a positive voltage of a proper level to the drain electrode 114 thereby forming a channel in a portion (channel forming region 116) of the P−-type body region 104 close to the interface between the same and the gate insulating film 106. Thus, a switching operation of the VDMOSFET is achieved.
For example, the product Ron·Qg of the on-resistance Ron and the gate charge quantity Qg of the VDMOSFET is employed as an index of the switching performance of the VDMOSFET, and the semiconductor device can achieve the switching operation at a higher speed as the product Ron·Qg is reduced.
In the semiconductor device 100 shown in FIG. 9, the on-resistance Ron3 of the VDMOSFET corresponds to resistance between the source wire 111 and the drain electrode 114, such as combined resistance of channel resistance Rch2 in the channel forming region 116 and epi-resistance Repi2 in the N−-type region 103, for example.
On the other hand, the gate charge quantity Qg3 of the VDMOSFET corresponds to the quantity of charges stored in a gate capacitance Cg3 (combined capacitance of the capacitance Cox4 of the gate insulating film 106 held between the gate electrode 107 and the portion of the N−-type region 103 on the bottom surface and the side surface of the gate trench 105, the capacitance Cox5 of the gate insulating film 106 held between the gate electrode 107 and the N+-type source region 108 and the capacitance Cdep3 of a depletion layer 115 spreading from the interface between the N−-type region 103 and the P−-type body region 104). In the semiconductor device 100, a high-speed switching operation of the VDMOSFET can be achieved if the product Ron3·Cg3 can be reduced.
As shown in FIG. 10, however, the on-resistance Ron3 and the gate capacitance Qg3 are in the so-called trade-off relation, such that the former is increased when the latter is reduced and vice versa. In order to reduce the product Ron3·Qg3, therefore, one of the on-resistance Ron3 and the gate capacitance Qg3 must be reduced, while preventing increase of the other.
The on-resistance Ron3 of the semiconductor device 100 can be reduced by reducing either the channel resistance Rch2 or the epi-resistance Repi2.
In order to reduce the on-resistance Ron3, the thickness of the gate insulating film 106 may be reduced, for example. If the thickness of the gate insulating film 106 is reduced, however, a voltage exceeding the withstand voltage of the gate insulating film 106 may be applied between the gate and the drain upon voltage application to the drain electrode 114, to result in dielectric breakdown of the gate insulating film 106. In order to prevent such dielectric breakdown, the thickness of the gate insulating film 106 cannot be reduced below a certain level, and hence the on-resistance Ron3 of the semiconductor device 100 cannot be sufficiently reduced. Therefore, it has been difficult to prepare a low-voltage semiconductor device drivable at a low voltage.